About us
We are searching for talented individuals who are driven to tackle the most ambitious goal of our time - building the computer hardware that enables the development of safe artificial general intelligence. See more at fathomradiant.co/aboutus
In our people, we above all value kindness, a scout mindset, a focus on improvement, and prioritising to get the right things done. We aim to help build one of the most transformative technologies in the world, with massive social and ethical implications. We think this makes representation even more important, and we are actively striving to have a range of diverse perspectives on our team.
This role
We’re seeking to fill multiple Packaging roles covering standard IC packaging, thermal management, and advanced packaging (e.g. 2.5 and 3D integration). Candidates with domain expertise in one or multiple of these areas are encouraged to apply. The scope of the roles will be determined by the background of the persons hired. As an Advanced Packaging Engineer at Fathom Radiant you will solve interdisciplinary packaging challenges, collaborating closely with colleagues from other disciplines (epitaxy, optoelectronics fabrication, optics, IC design, systems integration) to enable novel optoelectronic hardware for machine learning.
Areas of Contribution
Develop packaging designs to support and address digital interfaces, power integrity, and thermal considerations while not sacrificing optical performance. This potentially includes initial design concept, thermal, mechanical, and electrical (DC and RF) analysis and optimization, and manufacturing feasibility at die, substrate and assembly level
Design high performance substrates for signal and power distribution, mechanical stability, and thermal management
Manage thin film stresses, CTE mismatch, thermal and mechanical cycling, vibration and other environmental stressors
Develop advanced 2.5D and 3D microelectronic packaging solutions for next generation digital, mixed-signal, and analog silicon CMOS electronics with integrated III-V (GaAs, InP, GaN) components
Develop packaging designs and manufacturing process flows to allow DBI, microbumping, BGA, LGA and/or other integration technologies for wafer-to-wafer and chip-to-wafer stacks.
Assist with the documentation for product components, including models, production drawings, inspection criteria, etc.
Manage and collaborate with contract manufacturers for specification, fabrication and evaluation of the design and manufacturing processes
Evaluate designs for manufacturability and reliability; oversee metrology and failure analysis of packaging components
Some travel (<10%) may be required
Requirements
BS, MS or PhD in electrical engineering, physics, materials science or related discipline, or equivalent knowledge.
Minimum of 5 years of relevant experience in ASIC/GPU/CPU or optoelectronics packaging, substrate design, 2.5D and 3D microelectronics packaging, and/or thermal and mechanical package design.
Experience with wafer and chip integration technologies, from mainstream to state-of-the-art.
Knowledge of multi-physics simulation tools (ANSYS, COMSOL), high frequency and electromagnetic simulation tools (ADS, ANSYS HFSS), and 3D CAD mechanical drawing environment.
Experience with Cadence SiP Layout.
Knowledge of basic statistical process control and/or design of experiments principles.
Expertise in production packaging design, having previously transferred designs to manufacturing.
Working knowledge of microelectronic packaging test equipment.
Ability to work with vendors to develop state-of-the-art package solutions.
Experience in thermal, mechanical, electrical and environmental characterization and reliability testing; familiarity with failure analysis and package qualification.
Nice-to-haves
Familiarity with nano/microelectronics semiconductor fabrication and back end of line (BEOL) processing.
Working knowledge of signal requirements for multi-bit busses, such as DDR4/3, and high-speed serial interfaces such as PCIe-gen4/3.
Lab experience with high speed electrical measurements and test equipment.
Experience developing in-line packaging test equipment.
Experience with Computational Fluid Dynamics software tools, preferably with a background in modeling + experimental analysis.
Cadence SiP Layout Advanced WLP Option and Cadence Allegro.
Indicative salary range for this role: $90,000 - $150,000
If this sounds like you, we invite you to apply to come join us in our office in Boulder, CO. For all roles, we target market salaries, with an additional benefits package. Our comprehensive benefits include startup equity, medical expenses coverage (including extra coverage for employees with a family).
We highly encourage submission of a brief cover letter, just tell us why you're here (using the form when you submit an application).